= NANDĪlternatively, the 4-gate version of the XOR gate can be used with an inverter. This construction entails a propagation delay three times that of a single NAND gate and uses five gates.

Making other gates by using NAND gates Ī NAND gate is a universal gate, meaning that any other gate can be represented as a combination of NAND gates.Īn XNOR gate is made by considering the disjunctive normal form A ⋅ B + A ¯ ⋅ B ¯, noting from de Morgan's Law that a NAND gate is an inverted-input OR gate. As the only configuration of the two inputs that results in a low output is when both are high, this circuit implements a NAND (NOT AND) logic gate. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and Vdd (voltage source), bringing the output high. If both of the A and B inputs are low, then neither of the NMOS transistors will conduct, while both of the PMOS transistors will conduct, establishing a conductive path between the output and Vdd (voltage source), bringing the output high.

In CMOS logic, if both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and Vss (ground), bringing the output low. It has the following truth table:Ī CMOS transistor NAND element.

Xnand transistor gate